chisel3

Chisel: A Modern Hardware Design Language

Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions

An exquisite superscalar RV32GC processor.

Lectures for the Agile Hardware Design course in Jupyter Notebooks

Provides dot visualizations of chisel/firrtl circuits

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

Yet another toy CPU.

RISC-V CPU Labs in Chisel

NucleusRV (RV32-IMAFC) - A 32-bit 5 staged pipelined risc-v core.

Learning how to make RISC-V 32bit CPU with Chisel

educational microarchitectures for risc-v isa

A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code to values dumped by simulators is now possible thanks to Tywaves!

Documentation for YatCPU

vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器

Chisel library for Unum Type-III Posit Arithmetic

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.

Wrappers for open source FPU hardware implementations.

Quasar 2.0: Chisel equivalent of SweRV-EL2

Chisel implementation of Neural Processing Unit for System on the Chip