ASIC implementation flow infrastructure, successor to OpenLane
-
Updated
Aug 28, 2026 - Python
ASIC implementation flow infrastructure, successor to OpenLane
Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
Gate-level visualization generator for SKY130-based chip designs.
🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation
Minimal multimodal temporal sparse-query BEV POC for nuScenes/OpenLane with ONNX and TensorRT validation
Open educational toolkit for semiconductor device physics, compact modeling (BSIM4), SPICE analysis, reliability evaluation, and VLSI physical design.
Educational GPU platform - Democratizing GPU building with complete compute + graphics pipelines
An integrated educational framework covering semiconductor physics, circuit design, fabrication processes, and testing — from fundamentals to advanced practical applications. (物性・回路・プロセス・設計・テストを貫く一貫教育体系。基礎から応用・実践までを体系的に整理)
Universal Edge AI ASIC: Open-Source Silicon Accelerator for LLMs (llama.cpp GGUF Q4_K/IQ) & Diffusion DiT (Flux, SDXL) in SkyWater SKY130 130nm CMOS.
TinyTapeout GDS blackbox macro testing
Educational project that explores the AITL control architecture (PID × FSM × LLM) from Python modeling to ASIC implementation using Verilog, OpenLane, Magic, and ngspice.
RTL-to-GDS physical design of a parameterized MAC accelerator using open-source ASIC tools (Yosys, OpenLane, Sky130)
Tiny Tapeout TTSKY26c (sky130A): on-chip metastability characterizer -- ring-osc async data + 41-tap delay line + dual-sample witness FFs; raw UART stream for tau/W and MTBF extraction
Python client for TheCarApi — live car auction inventory from Copart, OpenLane, Auto1, Encar, eCarsTrade, Schadeautos and CarVector
To associate your repository with the openlane topic, visit your repo's landing page and select "manage topics."