cpu-cache

CoreFreq : CPU monitoring and tuning software designed for the 64-bit processors.

CPU INFOrmation library (x86/x86-64/ARM/ARM64, Linux/Windows/Android/macOS/iOS)

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs

The CacULE CPU scheduler is based on interactivity score mechanism. The interactivity score is inspired by the ULE scheduler (FreeBSD scheduler).

A survey on architectural simulators focused on CPU caches.

uiomem is a Linux device driver for accessing a memory area outside the Linux Kernel management from user space.

C++ library for storing objects of different types contiguously

CPU cache emulator (LRU)

CPU Cache line invalidation using Golang primitives

Data Oriented Design (DOD) vs. Object Oriented Design (OOD) in action with performance stats.

Returns your current CPU cache line size in bytes

A fairly fast c based prime calculator. Calculates in parallel & sequentially

MIPT-V Pipeline Flowchart Visualizer

cpu-simulator-cache-layers written in c++

Checking of cpu caches associativity

🐳 A Dockerized version of GCC-SLO (Suggestions for Locality Optimizations)

Multi-core CPU cache hierarchy simulator in C++20 — L1/L2/L3 with MESI coherency, LRU/FIFO/Random eviction, false sharing demo, trace-driven mode. 27 tests.

A lightweight, low-level C++ micro-benchmarking tool designed to accurately measure L1 data cache latency using hardware-aligned pointer chasing to prevent CPU prefetching and speculative execution.

Low-level programming assignments, "Low-Level Programming" (TDT4258) course, fall 2023.

Benchmark and visualization of CPU cache-hierarchy effects on memory-access latency (random vs. sequential), exposing L1/L2/L3 boundaries.