Toolset update: Fadsv7, x64/ARM64 phase 2, 48/64-core VMs - #6370
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Stephan T. Lavavej (StephanTLavavej) merged 16 commits intoJul 21, 2026
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Test_x86, Test_x64_ASan, Test_x86_ASan remain Slow. Test_x64 remains Fast.
Slow pool: 32 VMs, each 64-core. We use 10 VMs in Phase 3 to test x86, so this gives us throughput for 3 PRs. Medium pool: 13 VMs, each 48-core. We use 4 VMs in Phase 1, so this gives us throughput for 3 PRs. (Phase 1 is very fast, so the throughput is really higher.) Fast pool: 21 VMs, each 48-core. We use 10 VMs in Phase 2 to test x64, so this gives us throughput for 2 PRs. ARM64 pool: 32 VMs, each 64-core. We use at most 10 VMs simultaneously (2 in Phase 1, 10 in Phase 2, 10 in Phase 3), so this gives us throughput for 3 PRs.
…r 64-core). This will make it obvious if resizing works. 16 cores should be plenty for image setup.
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Pull request overview
Updates CI infrastructure with larger VM pools and a phased architecture-testing workflow.
Changes:
- Adds the Fadsv7 pool and enlarges existing pool VMs.
- Splits CI into initial-build, primary-test, and secondary-test phases.
- Uses native ARM64/ARM64EC builds and pool-specific work roots.
Show a summary per file
| File | Description |
|---|---|
azure-pipelines.yml |
Implements phased CI dependencies and pool assignments. |
azure-devops/create-1es-hosted-pool.ps1 |
Adds Fadsv7 and separates prototype and pool VM sizes. |
azure-devops/config.yml |
Defines new pools and work roots. |
azure-devops/asan-pipeline.yml |
Uses the renamed slow-pool work root. |
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I'm mirroring this to the MSVC-internal repo. Please notify me if any further changes are pushed, otherwise no action is required. |
Zack Johnson (zacklj89)
approved these changes
Jul 20, 2026
Stephan T. Lavavej (StephanTLavavej)
merged commit Jul 21, 2026
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Overview
This adds an Fadsv7 pool, which is the fastest available x64 SKU: non-SMT Zen 5, with NVMe temp storage.
And now that we have more and larger pools, this restructures the dependencies between stages. I'm replacing a complicated dependency graph with simpler phases, where each phase needs to succeed before the next phase begins.
We start with a Phase 1 of initial builds, which verify that the PR conforms to our formatting and validation requirements, that the STL builds for all architectures (with
/analyze), and that the tests successfully configure. We now rely on ARM64 and ARM64EC native builds, and we don't bother with cross builds.Then we have a Phase 2 of primary test architectures, where x64 and ARM64 run simultaneously. Finally, we have a Phase 3 of secondary test architectures: x86 and ARM64EC. (Previously, we gated x64 to run first, followed by x86, ARM64, and ARM64EC simultaneously.)
By spreading out the test architectures like this, we reduce each PR's maximum pressure on the pools (particularly the ARM64 pool). For the first time, I'm also giving the initial stages a dedicated pool, so even if the PR/CI system is under heavy load, initial checks won't be held up behind larger test runs.
For PRs with failing tests in x64, this will waste an ARM64 test run compared to the previous structure, but we still save the secondary test runs (which is better than other PR systems which I shall not discuss here). On the plus side, ARM64-only failures will now avoid wasting x86/ARM64EC test runs, and will deliver feedback faster.
I'm also changing our VMs to be larger: 48-core when we're limited by quota, 64-core when we're less constrained. The SKUs with temp storage (Fadsv7 and Dpdsv6) especially benefit from higher core counts. We'll unlock further gains when we improve long-running tests, which waste a lot of time at the end of each test pass with low parallelism.
I also had to change
create-1es-hosted-pool.ps1to prepare prototype VMs with only 16 cores, before imaging them to create the pools with larger VMs. I'm adding a comment explaining why we're doing this and why it works.Pool structure
If and when I can obtain more quota, we may simplify this pool structure in the future.
Commits
$VMSizeinto$ProtoVMSize(16-core) and$PoolSkuName(48-core or 64-core).