Sanmina's 1.6T Transceiver Platform at OFC2026

Co-Packaged Optics Race: Strategic Approaches from NVIDIA and Broadcom: Co-packaged optics (CPO) is gaining significant attention as the next architecture for next-generation switching. The shift toward co-packaged optics is also reshaping competitive positioning among semiconductor vendors. This article examines the differing approaches of NVIDIA and Broadcom, with further detail available in IDTechEx's latest report, "Co-Packaged Optics (CPO) 2026-2036: Technologies, Market, and Forecasts". http://dlvr.it/TRQWSR

Powering the next generation of designs takes more than components—it takes the right partners. At APEC 2026, DigiKey is bringing together power solutions from leading suppliers to help engineers tackle efficiency, performance, and reliability challenges. The booth will feature product demos from Microchip Technology Inc., Nichicon (America) Corporation, Qorvo, Inc., and STMicroelectronics, highlighting real-world applications and the technologies driving modern power design. From power management to system-level innovation, these solutions are shaping what’s next. 👉 Learn more: https://lnkd.in/eWmNkqGZ #APEC2026 #PowerElectronics #Engineering #Electronics #DigiKey #Microchip #Nichicon #STMicroelectronics

Advanced Packaging Evolution: Si/RDL Interposers As semiconductor designs push beyond traditional scaling, advanced packaging technologies are becoming critical to achieving higher performance, bandwidth, and integration. Three key approaches: 2.5D with Silicon Interposer Enables ultra-high density interconnects Ideal for high-performance systems like HBM integration Supports fine line/space scaling for maximum bandwidth FOCoS (Fan-Out Chip-on-Substrate) Uses RDL interposers for flexible routing Balances performance and cost Supports multiple redistribution layers (RDLs) for advanced memory integration FOCoS-B (With Bridge Interposers) Combines RDL + bridge die for ultra-high density connections Enables localized high-speed communication between dies Optimized for next-gen heterogeneous integration The shift from silicon interposers to RDL and bridge-based architectures highlights the industry's move toward cost-efficient, scalable, and high-performance packaging solutions. Advanced packaging is no longer an option it’s a necessity for modern chip design. #Semiconductor #VLSI #AdvancedPackaging #ChipDesign #HBM #Electronics

As semiconductor devices become more complex and power-sensitive, test systems must deliver more than just accuracy. They must also provide speed, synchronization, and scalability. That’s why ADLINK introduced our latest PXI Express solutions: 🔹 𝗣𝗫𝗜𝗲-𝟵𝟵𝟬𝟴 8-CH SMU for parallel high-precision sourcing & measurement 🔹 𝗣𝗫𝗘𝗦-𝟮𝟱𝟵𝟲 chassis for high-bandwidth, flexible system architecture Designed for device characterization and production validation, these platforms help engineers build modular, production-ready test systems with greater efficiency and control. 🔗 Learn more: https://okt.to/N9CwR2 #PXI #TestAndMeasurement #Semiconductor #Engineering

Adeia Expands Partnership with United Microelectronics Corporation (UMC) We are pleased to expand and extend our partnership with UMC, a respected leader in semiconductor manufacturing, said Dr. Mark Kokes, chief revenue officer of Adeia. “Our innovations in hybrid bonding and advanced interconnect technologies are helping shape the future of semiconductors. This agreement reflects the strength of our IP portfolio and our commitment to supporting UMC as they continue to drive advancements in 3D integration and heterogeneous packaging. 𝐑𝐞𝐚𝐝 𝐌𝐨𝐫𝐞: https://lnkd.in/dS78x27G #3Dintegration #Adeia #Microelectronics #news #ReadMagazine #Semiconductorandelectronics #semiconductorpackaging #UnitedMicroelectronicsCorporation

We’re proud to share that Adeia’s RapidCool™ technology has been honored with an Electronics Excellence Award at the embedded world Exhibition&Conference. Thank you to Electronic Specifier Ltd for the recognition���and congratulations to our semiconductor research team for pushing the boundaries of innovation in thermal management. As AI and HPC workloads drive unprecedented power densities, thermal management has become one of the most critical barriers to scaling compute. RapidCool™ is Adeia’s direct-to-chip liquid cooling solution, engineered to efficiently remove heat at the source and reduce overall package temperatures—enabling higher-performance AI chipsets in next-generation data centers. Innovation that unlocks what’s next in compute. #AI #HPC #Semiconductors #DataCenter #ComputeScaling

🚀 The 3nm Frontier: More Than Just Shrinking Transistors Design at the leading edge is no longer just about density; it’s about a fundamental shift in how we manage the physics of computation. As we move deep into the 3nm node and beyond, we aren't just placing cells—we are orchestrating energy and heat at a near-atomic scale. Here are the three architectural shifts currently redefining our field: 1. The Gate-All-Around (GAA) Revolution 🔌 The transition from FinFET to Nanosheet/GAA is the most significant structural change in a decade. By wrapping the gate around all four sides of the channel, we’ve gained unprecedented electrostatic control. The Impact: Drastically lower sub-threshold leakage and higher drive currents at lower voltages—essential for the next generation of high-performance mobile SoCs. 2. The Power Flip: Backside PDN ⚡ Routing congestion has long been the bottleneck of physical design. The emergence of Backside Power Delivery Networks (BSPDN) is a literal "flip" in our thinking. The Innovation: Moving power rails to the underside of the silicon separates the "delivery" from the "signaling." The Result: This eliminates top-metal congestion, slashes IR Drop, and opens up new degrees of freedom for cell density. 3. Precision Signoff in a Non-Linear World 📉 At sub-0.7V levels, traditional timing models are no longer sufficient. We are moving toward Liberty Variation Formats (LVF) to account for non-Gaussian distributions and extreme process sensitivity. The Challenge: Closing timing across hundreds of MCMM (Multi-Corner Multi-Mode) scenarios while balancing thermal-aware placement. In the world of Synthesis and Static Timing Analysis, we are the gatekeepers of this complexity. Our goal isn't just to hit a frequency; it’s to ensure reliability in an increasingly volatile physical environment. #VLSI #Semiconductors #3nm #STA #PhysicalDesign #ElectronicEngineering #Innovation

CEA-Leti unveils cutting-edge microelectronics reliability research at IRPS 2026, covering GaN, FD-SOI, RF, and 3D integration. #Microelectronics #Semiconductors #IRPS2026 #ChipDesign FAMES Pilot Line https://lnkd.in/g8DnQBPW

#SiliconPhotonics Race Intensifies as #TSMC Targets 2026 #COUPE Production, #Samsung Eyes 2029 #CPO Turnkey As #GPUs become more advanced, they need faster ways to move data between chips. Because of this, optical (light-based) communication is becoming more important. Big companies like #TSMC are also getting involved. According to Commercial Times, TSMC plans to start mass production of its #COUPE silicon photonics platform in 2026, which is an important step toward using co-packaged optics (#CPO). TSMC explains that COUPE (Compact Universal Photonic Engine) uses a technology called #SoIC-X stacking. This allows an electrical chip to be placed directly on top of a photonic (light-based) chip. This design reduces resistance between the chips and improves power efficiency compared to older methods. The plan is to first qualify this technology for small plug-in optical modules in 2025, and then use it in #CoWoS-based co-packaged optics systems by 2026. Check full insights via the link below https://lnkd.in/gW-PmbQ4